1. Field of the Invention
This invention relates to semiconductor devices and more particularly to memory devices and the methods of manufacture thereof.
2. Description of Related Art
U.S. Pat. No. 5,204,542 of Namaki et al "Nonvolatile Semiconductor Memory Device of Shared Contact Scheme Not Having Inclined Wiring" uses diffused layers in silicon and polysilicon for shared contacts.
Sharing of the same contacts by two cells is not sufficient because the contact and relative design rule will limit the cell size.
FIG. 17 shows a prior art plan view of a ROM, EPROM or Flash memory device. The prior art device of FIG. 17 includes horizontally disposed word lines WL0, WL1, WL2, and WL3 and bit lines BL0, BL1, BL2, and BL3; bit line common contacts X1, X2, X3, X4, XS, X6, X7 and X8; and field oxide elements 91, 92, 93 94, 95 and 96.
FIG. 18 shows a prior art plan view of a DRAM. The horizontally disposed word lines WL0, WL1, WL2, and WL3 and vertical disposed bit line drain contacts BL0, BL1, and BL2. There are contact regions X1, X2, and X3 which connect to bit lines BL0, BL1, and BL2.
The DRAM memory nodes N1, N2, N3 N4, N5 and N6 connect to the capacitors C1, C2, C3, C4, C5 and C6.